- Darko Zivanovic:
Memory Systems for High-Performance Computing: The Capacity and Reliability Implications. Universitat Politecnica de Catalunya, 2018. Supervisor: Petar Radojković
- Milan Radulovic:
Memory Bandwidth and Latency in HPC: System Requirements and Performance Impact. Universitat Politecnica de Catalunya, 2019. Supervisor: Petar Radojković
- Kazi Asifuzzaman:
Performance evaluation of STT-MRAM main memory in HPC and real-time systems with WCET implications. Universitat Politecnica de Catalunya, 2019.
Supervisor: Petar Radojković
- D1.4: Data Management Plan for pilot on Open Research Data [PDF]
- D2.1: Report on the ExaNoDe miniapplications [PDF]
- D2.2: Report on the ExaNoDe architecture design guidelines [PDF]
- D2.3: Report and best practices on porting of the mini-applications to the ExaNoDe architecture [PDF]
- D2.4: ExaNoDe Infrastructure Requirements [PDF]
- D2.5: Report on the performance bottlenecks of the state-of-the-art HPC platforms [PDF]
- D3.1: Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Analysis of the hardware system characteristics and design of a preliminary software implementation [PDF]
- D3.2: Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Advanced implementation customized for ExaNoDe architecture, interconnect, operating system [PDF]
- D3.6: Design of the ExaNoDe Firmware (report and initial prototype) [PDF]
- D3.7: Operating System Support for ExaNoDe [PDF]
- D5.2: HW-SW integration and tuning [PDF]
- D6.1: Project External Website, project flyer and social media presence [PDF]
- D6.2: Dissemination Strategy Document [PDF]
- D6.3: Initial Project Press Release [PDF]
Recent Overview Presentations
- Manolis Katevenis:
I/O, today, is Remote (block) Load/Store, and must not be slower than Compute, any more. Invited talk, PER 2018 workshop (PERspectives on the Future of Computing), within the HiPEAC Computing Systems Week (CSW), Gothenburg, Sweden, 23. 5. 2018.
[PDF Document] [YouTube Video]
- Denis Dutoit:
Silicon interposer integration combined with novel system architecture for energy-efficient and heterogeneous compute node: the ExaNoDe solution. Workshop on “Post Moore Interconnects” at ISC 2018, Frankfurt (M), Germany, 28.6.2018
Presentations from the workshop “ExascaleHPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects” in January 2018
- N. Kallimanis, M. Marazakis, E. Skordalaki:
Use-cases for Remote Memory in the UNIMEM Architecture
- K. Pouget, A. Mouzakitis, R. Dimitrov, A. Rigo, D. Raho:
Virtualization for HPC
- P.Y. Martinez, D. Dutoit, A. Philippe, P. Vivet, D.Drouin, Y. Beilliard:
3D-IC Design Solution for Modular Integration of Chiplet over Silicon Interposer
- P. Mroszczyk, V. Pavlidis:
Ultra-Low Swing Transceiver for Energy Efficient Communication in 2.5-D Integrated Systems
- B. Chalios:
ExaNoDe Programming Environment to Exploit ARM, UNIMEM and FPGAs
Presentations from the workshop “Towards Exascale HPC systems: Co-design and Technology development within the EuroEXA, ExaNeSt, ExaNoDe and EcoScale projects” in May 2018
- R. Dimitrov, K. Pouget:
Virtualization technologies in modern HPC systems
- N. Kallimanis:
A Flexible & Efficient Shared Memory Abstraction with Minimal HW Assistance
ExaNoDe Open Source Strategy
ExaNoDe endorsed the EU Commission Open Source strategy and made the contributions described below.
BSC released its OmpSs-2 parallel programming model as part of the Nanos6 runtime. This support for clusters was publicly released under GNU GPLv3 within the 19.06 version of OmpSs-2. The repository is available at this link.
A second open source release regards instead PROFET, an analytical model that predicts how an application’s performance and energy consumption changes when it is executed on different memory systems. The repository exists at this address but the code has not been uploaded yet, it will be available soon.
ETHZ opened many of the hardware intellectual properties (IPs) developed in the project as part of the PULP platform (https://pulp-platform.org) under the liberal, Apache-derived SolderPad license. These include among others also many IPs used to build the internal interconnects used within and between the ExaConv clusters (APB, AXI bridges that can be found here and here), DMAs, interrupt controllers. IPs are distributed in the form of synthesizable HDL code in SystemVerilog, C code, and related documentation. The software-only components have been released with Apache 2 license.
Forschungszentrum Jülich has released the mini-applications – namely HydroC, miniFE, miniKKR and BQCD – at the following address under GNU GPLv2, GNU GPL v3, LGPL, CeCILL and BSD license. These are self-contained and based on real-life applications that have been developed and ported to the architecture via the programming models and communication APIs.
Virtual Open Systems developed a QEMU extension for virtual machine periodic checkpointing. A repository including all the changes is available at this address. The code is released under GNU GPLv2. Virtual Open Systems is working on a companion page in its website that instructs on how to compile and reproduce the periodic checkpointing of an ARMv8 virtual machine. The page will be reachable from this address.
Links of interest: