Publications

2015


2016

  • Zivanovic, M. Radulovic, G. Llort, D. Zaragoza, J. Strassburg, P. Carpenter, P. Radojkovic, E. Ayguadé Parra:
    “Best Paper Award at MEMSYS 2016”: Large-Memory Nodes for Energy Efficient High-Performance Computing, in Proceedings of MEMSYS 2016.
    [OpenAIRE] [UPCommons].
  • Drebes, A. Pop, K. Heydemann, A. Cohen, N. Drach:
    “Best Paper Award at PACT 2016”: Scalable Task Parallelism for NUMA – A Uniform Abstraction for Coordinated Scheduling and Memory Management, in Proceedings of PACT 2016.
    [OpenAIRE] [HAL-Inria]
  • Drebes, J.-B. Bréjon, A. Pop, K. Heydemann, A. Cohen:
    Language-Centric Performance Analysis of OpenMP Programs with Aftermath, in Proceedings of IWOMP 2016 (LNCS 9903).
    [OpenAIRE] [HAL-UPMC]
  • Drebes, A. Pop, K. Heydemann, A. Cohen:
    Interactive visualization of cross-layer performance anomalies in dynamic task-parallel applications and systems, in Proceedings of ISPASS 2016.
    [OpenAIRE] [HAL-Inria]
  • Zivanovic, M. Radulovic, G. Llort, D. Zaragoza, J. Strassburg, P.  Carpenter, P. Radojkovic, E. Ayguadé Parra:
    Performance Impact of a Slower Main Memory – A case study of STT-MRAM in HPC, in Proceedings of MEMSYS 2016.
    [OpenAIRE] [UPCommons]

2017

  • Zivanovic, M. Pavlovic, M. Radulovic, H. Shin, J. Son, S. McKee, P. Carpenter, P. Radojkovic, E. Ayguade:
    Main memory in HPC: do we need more, or could we live with less? ACM Transactions on Architecture and Code Optimization (TACO) vol 14 issue
    [OpenAIRE] [UPCommons]
  • Asifuzzaman, R. Sánchez Verdejo, P. Radojkovic:
    Enabling a Reliable STT-MRAM Main Memory Simulation, in Proceedings of MEMSYS 2017.
    [OpenAIRE] [UPCommons]
  • Rigo, C. Pinto, K. Pouget, D. Raho, D. Dutoit, P.-Y. Martinez, C. Doran, L. Benini, I. Mavroidis, M. Marazakis, V. Bartsch, G. Lonsdale, A. Pop, J. Goodacre, A. Colliot, P. Carpenter, P. Radojkovic, D. Pleiter, D. Drouin, B. Dupont de Dinechin:
    Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach, in Proceedings of EUROMICRO DSD 2017.
    [OpenAIRE] [UPCommons]
  • Conti, R. Schilling, P. D. Schiavone, A. Pullini, D. Rossi, F. K. Gürkaynak, M. Muehlberghuber, M. Gautschi, I. Loi, G. Haugou, S. Mangard, L. Benini:
    An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Transactions on Circuits and Systems I: Regular Papers (Vol 64, Issue 9, Sept. 2017)
    [OpenAire]

2018

  • Conti, L. Cavigelli, G. Paulin, I. Susmelj, L. Benini:
    Chipmunk: A systolically scalable 0.9 mm2, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference, in Proceedings of 2018 IEEE Custom Integrated Circuits Conference (CICC)
    [OpenAire]
  • Panagiota Fatourou, Nikolaos D. Kallimanis:
    Lock Oscillation: Boosting the Performance of Concurrent Data Structures, in Proceedings of OPODIS 2017.
    [OpenAIRE] [Presentation (PDF)]
  • Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
    Mismatch Compensation Technique for Inverter-Based CMOS Circuits, in Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018)
    [OpenAire] [U. Manchester Repository]
  • Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
    Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems, in Proceedings of 2018 International Symposium on Quality Electronic Design (ISQeD 2018)
    [U. Manchester Repository]
  • Panagiota Fatourou, Nikolaos D. Kallimanis, Thomas Ropars:
    An EfficientWait-free Resizable Hash Table.
    [to appear]
  • Milan Radulovic, Kazi Asifuzzaman, Paul Carpenter, Petar Radojković, Eduard Ayguadé:
    HPC benchmarking: scaling right and looking beyond the average.
    [to appear]

Public deliverables

  • D1.4: Data Management Plan for pilot on Open Research Data [PDF]
  • D2.1: Report on the ExaNoDe miniapplications [PDF]
  • D2.2: Report on the ExaNoDe architecture design guidelines [PDF]
  • D2.3: Report and best practices on porting of the mini-applications to the ExaNoDe architecture [PDF]
  • D2.4: ExaNoDe Infrastructure Requirements [PDF]
  • D2.5: Report on the performance bottlenecks of the state-of-the-art HPC platforms [PDF]
  • D3.1: Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Analysis of the hardware system characteristics and design of a preliminary software implementation [PDF]
  • D3.2: Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Advanced implementation customized for ExaNoDe architecture, interconnect, operating system [PDF]
  • D3.6: Design of the ExaNoDe Firmware (report and initial prototype) [PDF]
  • D3.7: Operating System Support for ExaNoDe [PDF]
  • D5.2: HW-SW integration and tuning [PDF]
  • D6.1: Project External Website, project flyer and social media presence [PDF]
  • D6.2: Dissemination Strategy Document [PDF]
  • D6.3: Initial Project Press Release [PDF]

Selected Presentations

Recent Overview Presentations

  • Manolis Katevenis:
    I/O, today, is Remote (block) Load/Store, and must not be slower than Compute, any more. Invited talk,  PER 2018 workshop  (PERspectives on the Future of Computing), within the HiPEAC Computing Systems Week (CSW), Gothenburg, Sweden, 23. 5.  2018.
    [PDF Document] [YouTube Video]
  • Denis Dutoit:
    Silicon interposer integration combined with novel system architecture for energy-efficient and heterogeneous compute node: the ExaNoDe solution. Workshop on “Post Moore Interconnects”  at ISC 2018, Frankfurt (M), Germany, 28.6.2018
    [PDF Document]

Presentations from the workshop “ExascaleHPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects” in January 2018

  • N. Kallimanis, M. Marazakis, E. Skordalaki:
    Use-cases for Remote Memory in the UNIMEM Architecture
    [PDF]
  • K. Pouget, A. Mouzakitis, R. Dimitrov, A. Rigo, D. Raho:
    Virtualization for HPC 
    [PDF]
  • P.Y. Martinez, D. Dutoit, A. Philippe, P. Vivet, D.Drouin, Y. Beilliard:
    3D-IC Design Solution for Modular Integration of Chiplet over Silicon Interposer 
    [PDF]
  • P. Mroszczyk, V. Pavlidis:
    Ultra-Low Swing Transceiver for Energy Efficient Communication in 2.5-D Integrated Systems
    [PDF]
  • B. Chalios:
    ExaNoDe Programming Environment to Exploit ARM, UNIMEM and FPGAs
    [PDF]