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Press release: ExaNode project produced groundbreaking compute unit prototype for Exascale

The ExaNode Project finished successfully in summer 2019 The project has built a groundbreaking compute unit prototype paving the way to tomorrow’s  exascale supercomputers, those capable of performing a billion billion calculations per second, or ten times faster than today’s most powerful computers. Read more in our general and technical press releases: Press release – with technical details (PDF) Press release – for the general public (PDF)

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Workshop “EuroExaScale: Towards European Exascale HPC”, January 21-23 2019, Valencia, Spain

Exascale computing workshop accepted for HiPEAC2019:  “EuroExaScale: Towards European Exascale HPC” The workshop  “EuroExaScale: Towards European Exascale HPC”will take place during the HiPEAC 2019 conference, January 21-23 2019, Valencia, Spain. It is the 4thjoint workshop organized by the projects ExaNoDe, ExaNeST, ECOSCALE and EuroExa.

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Exascale computing workshop, October 8-9 2018, Vicenza, Italy

Exascale computing workshop:  “Experiences and best practices for porting applications to emerging HPC architectures and platforms” Share experiences and achievements around the various European platforms developed by the ExaNeSt, ExaNoDe, Ecoscale and EuroExa projects. October 8-9 2018,  co-located with the CAE Conference 2018 in Vicenza, Italy. This workshop aims to provide a forum for vanguard users and developers in the HPC arena to share their experiences and achievements around the various European platforms developed by the ExaNeSt, ExaNoDe, Ecoscale and EuroExa projects. Whether you are designers of new hardware architectures or system components; software or application developers; or users that [...]

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VOSYS presentation on virtualization for HPC at COMPAS

Kevin Pouget from Virtual Open Systems presented the ExaNoDe work on virtualization at the COMPAS conference: OpenCL accelerator API remoting for HPC computing, and virtual machine live and incremental checkpointing. He presented a poster and gave a talk in the industrial session of the COMPAS conference. COMPAS, a French-speaking conference aimed at gathering senior researchers with PhD students and industrials around the topics of parallel computing, systems and architectures, took place in Toulouse, France, 3-6th of July.

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EuroPar 2018, August 29-31, Turin

The paper “HPC benchmarking: scaling right and looking beyond the average” by ExaNoDe partner BSC was accepted for EuroPar 2018 taking place in Turin, August 29-31, 2018. Euro-Par is the prime European conference covering all aspects of parallel and distributed processing, ranging from theory to practice, from small to the largest parallel and distributed systems and infrastructures, from fundamental computational problems to full-fledged applications, from architecture, compiler, language and interface design and implementation, to tools, support infrastructures, and application performance aspects. Euro-Par’s unique organization into topics provides an excellent forum for focused technical discussion, as well as interaction with a [...]

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HPC benchmarking: scaling right and looking beyond the average

The paper “HPC benchmarking: scaling right and looking beyond the average” by Milan Radulovic, Kazi Asifuzzaman, Paul Carpenter, Petar Radojković and Eduard Ayguadé from ExaNode Partner BSC will be presented at EuroPar 2018 in Turin, August 2018. Abstract: Designing a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads, and which quantifies the main performance bottlenecks. In this paper, we execute seven production HPC applications on a production HPC platform, and analyse key performance bottlenecks: FLOPS performance and memory bandwidth congestion, [...]

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An EfficientWait-free Resizable Hash Table

The paper “An EfficientWait-free Resizable Hash Table” by Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH has been accepted by 30th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2018) taking place from July 16-18 in Vienna. The paper builds on FORTH’s work in ExaNoDe on Lock Oscillation. Abstract: This paper presents an efficient wait-free resizable hash table. To achieve high throughput at large core counts, our algorithm is specifically designed to retain the natural parallelism of concurrent hashing, while providing wait-free resizing. An extensive evaluation of our hash table shows that it provides an unprecedented combination of [...]

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SPAA 2018, July 16-18, Austria, Vienna

Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH will present a paper on “An EfficientWait-free Resizable Hash Table” at the 30th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2018) taking place from July 16-18 in Vienna. SPAA is a concerence covering all areas of parallel algorithms and architectures, broadly construed, including both theoretical and experimental perspectives.

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Workshop “Towards Exascale HPC systems” @ European HPC Summit Week 2018

Workshop “Towards Exascale HPC systems” Co-design and Technology development within the EuroEXA, ExaNeSt, ExaNoDe and EcoScale projects. Thursday 31 May 2018, 14:30 - 18:30, co-located with the European HPC Summit Week 2018, Ljubljana, Slovenia Registration: http://www.eiseverywhere.com/europeanhpcsummitweek18 Download agenda as PDF Employing co-design to ensure technology developments that address the complete computing platform, the 4 projects address low-power, scalable and heterogeneous compute to meet the demands of Exascale computing. EuroEXA leads the System Software and Programming Environment activity, ExaNeSt develops innovative interconnects, storage, and packaging/cooling technologies. EcoScale focuses on integrating the acceleration capabilities of FPGAs. ExaNoDe develops heterogeneous, interposer-based, System-on-a-Chip (SoC) [...]

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isQED 2018, March 13-14, 2018, USA, Santa Clara

Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester will present a paper on "Mismatch Compensation Technique for Inverter-Based CMOS Circuits" at isQED 2018 in Santa Clara, USA (March 13-14, 2018). The 19th International Symposium on Quality Electronic Design (ISQED 2018) [link: http://www.isqed.org] is the premier interdisciplinary and multidisciplinary Electronic Design conference - bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve total design quality.

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ISCAS 2018, May 27-30, 2018, Florence, Italy

Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester will present a paper on "Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems" at ISCAS 2018 in Florence, Italy (May 27-30, 2018)The International Symposium on Circuits and Systems (ISCAS) [link: http://www.iscas2018.org] is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2018 focuses on the Art of Circuits and Systems to highlight the strong foundation in methodology and the integration of multidisciplinary [...]

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The paper “Mismatch Compensation Technique for Inverter-Based CMOS Circuits” was accepted for the isQED 2018 conference

The paper "Mismatch Compensation Technique for Inverter-Based CMOS Circuits" by  Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester was accepted for the isQED 2018 conference. Abstract: This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down [...]

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