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Press release: ExaNode project produced groundbreaking compute unit prototype for Exascale

The ExaNode Project finished successfully in summer 2019 The project has built a groundbreaking compute unit prototype paving the way to tomorrow’s  exascale supercomputers, those capable of performing a billion billion calculations per second, or ten times faster than today’s most powerful computers. Read more in our general and technical press releases: Press release – with technical details (PDF) Press release – for the general public (PDF)

Workshop “EuroExaScale: Towards European Exascale HPC”, January 21-23 2019, Valencia, Spain

Exascale computing workshop accepted for HiPEAC2019:  “EuroExaScale: Towards European Exascale HPC” The workshop  “EuroExaScale: Towards European Exascale HPC”will take place during the HiPEAC 2019 conference, January 21-23 2019, Valencia, Spain. It is the 4thjoint workshop organized by the projects ExaNoDe, ExaNeST, ECOSCALE and EuroExa.

Exascale computing workshop, October 8-9 2018, Vicenza, Italy

Exascale computing workshop:  “Experiences and best practices for porting applications to emerging HPC architectures and platforms” Share experiences and achievements around the various European platforms developed by the ExaNeSt, ExaNoDe, Ecoscale and EuroExa projects. October 8-9 2018,  co-located with the CAE Conference 2018 in Vicenza, Italy. This workshop aims to provide a forum for vanguard users and developers in the HPC arena to share their experiences and achievements around the various European platforms developed by the ExaNeSt, ExaNoDe, Ecoscale and EuroExa projects. Whether you are designers of new hardware architectures or system components; software or application developers; or users that [...]

VOSYS presentation on virtualization for HPC at COMPAS

Kevin Pouget from Virtual Open Systems presented the ExaNoDe work on virtualization at the COMPAS conference: OpenCL accelerator API remoting for HPC computing, and virtual machine live and incremental checkpointing. He presented a poster and gave a talk in the industrial session of the COMPAS conference. COMPAS, a French-speaking conference aimed at gathering senior researchers with PhD students and industrials around the topics of parallel computing, systems and architectures, took place in Toulouse, France, 3-6th of July.

EuroPar 2018, August 29-31, Turin

The paper “HPC benchmarking: scaling right and looking beyond the average” by ExaNoDe partner BSC was accepted for EuroPar 2018 taking place in Turin, August 29-31, 2018. Euro-Par is the prime European conference covering all aspects of parallel and distributed processing, ranging from theory to practice, from small to the largest parallel and distributed systems and infrastructures, from fundamental computational problems to full-fledged applications, from architecture, compiler, language and interface design and implementation, to tools, support infrastructures, and application performance aspects. Euro-Par’s unique organization into topics provides an excellent forum for focused technical discussion, as well as interaction with a [...]

HPC benchmarking: scaling right and looking beyond the average

The paper “HPC benchmarking: scaling right and looking beyond the average” by Milan Radulovic, Kazi Asifuzzaman, Paul Carpenter, Petar Radojković and Eduard Ayguadé from ExaNode Partner BSC will be presented at EuroPar 2018 in Turin, August 2018. Abstract: Designing a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads, and which quantifies the main performance bottlenecks. In this paper, we execute seven production HPC applications on a production HPC platform, and analyse key performance bottlenecks: FLOPS performance and memory bandwidth congestion, [...]

An EfficientWait-free Resizable Hash Table

The paper “An EfficientWait-free Resizable Hash Table” by Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH has been accepted by 30th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2018) taking place from July 16-18 in Vienna. The paper builds on FORTH’s work in ExaNoDe on Lock Oscillation. Abstract: This paper presents an efficient wait-free resizable hash table. To achieve high throughput at large core counts, our algorithm is specifically designed to retain the natural parallelism of concurrent hashing, while providing wait-free resizing. An extensive evaluation of our hash table shows that it provides an unprecedented combination of [...]

SPAA 2018, July 16-18, Austria, Vienna

Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH will present a paper on “An EfficientWait-free Resizable Hash Table” at the 30th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2018) taking place from July 16-18 in Vienna. SPAA is a concerence covering all areas of parallel algorithms and architectures, broadly construed, including both theoretical and experimental perspectives.

Workshop “Towards Exascale HPC systems” @ European HPC Summit Week 2018

Workshop “Towards Exascale HPC systems” Co-design and Technology development within the EuroEXA, ExaNeSt, ExaNoDe and EcoScale projects. Thursday 31 May 2018, 14:30 - 18:30, co-located with the European HPC Summit Week 2018, Ljubljana, Slovenia Registration: http://www.eiseverywhere.com/europeanhpcsummitweek18 Download agenda as PDF Employing co-design to ensure technology developments that address the complete computing platform, the 4 projects address low-power, scalable and heterogeneous compute to meet the demands of Exascale computing. EuroEXA leads the System Software and Programming Environment activity, ExaNeSt develops innovative interconnects, storage, and packaging/cooling technologies. EcoScale focuses on integrating the acceleration capabilities of FPGAs. ExaNoDe develops heterogeneous, interposer-based, System-on-a-Chip (SoC) [...]

isQED 2018, March 13-14, 2018, USA, Santa Clara

Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester will present a paper on "Mismatch Compensation Technique for Inverter-Based CMOS Circuits" at isQED 2018 in Santa Clara, USA (March 13-14, 2018). The 19th International Symposium on Quality Electronic Design (ISQED 2018) [link: http://www.isqed.org] is the premier interdisciplinary and multidisciplinary Electronic Design conference - bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve total design quality.

ISCAS 2018, May 27-30, 2018, Florence, Italy

Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester will present a paper on "Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems" at ISCAS 2018 in Florence, Italy (May 27-30, 2018)The International Symposium on Circuits and Systems (ISCAS) [link: http://www.iscas2018.org] is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2018 focuses on the Art of Circuits and Systems to highlight the strong foundation in methodology and the integration of multidisciplinary [...]

The paper “Mismatch Compensation Technique for Inverter-Based CMOS Circuits” was accepted for the isQED 2018 conference

The paper "Mismatch Compensation Technique for Inverter-Based CMOS Circuits" by  Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester was accepted for the isQED 2018 conference. Abstract: This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down [...]

The paper “Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems” was accepted for the ISCAS 2018 conference

The paper "Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems" by Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester was accepted for the ISCAS 2018 conference. Abstract: Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication, A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant [...]

Exascale HPC Workshop at HiPEAC 2018

On Tuesday 23rd January, the partners of the ExaNoDe, ExaNeSt, ECOSCALE and EuroEXA projects gathered at the HiPEAC conference in Manchester, UK, for the joint Exascale workshop. The day started with a well-attended keynote by John Goodacre, Professor of Computer Architectures at the University of Manchester and Director of Technology and Systems at ARM Ltd. Then the ExaNoDe, ExaNeSt and ECOSCALE partners presented their technological advances in 11 high-quality presentations. […]

Program of the Exascale HPC Workshop at HiPEAC 2018 has been published

The program of the Exascale HPC Workshop at HiPEAC 2018 has been published: Update: ExaNoDe presentations are online Tuesday 23 January 2018 full day (10:00-17:30) This Workshop (part of HiPEAC 2018) will present the main results from ExaNoDE and its two sibling projects, ExaNeSt, and EcoScale, which are at the end of their 2nd year, each; also, the newly-started follow-up FET-HPC project, EuroEXA, will present its plans for the next 3 years. The four projects cover, collectively, the following areas, which this Workshop will also cover: […]

Conference on Principles of Distributed Systems (OPODIS 2017), 18.-20.12.2017, Lisboa, Portugal.

Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH will present a paper on "Lock Oscillation: Boosting the Performance of Concurrent Data Structures". OPODIS is an open forum for the exchange of state-of-the-art knowledge on distributed computing and distributed computer systems. All aspects of distributed systems are within the scope of OPODIS. All aspects of distributed systems are within the scope of OPODIS, including theory, specification, design, performance, and system building. With strong roots in the theory of distributed systems, OPODIS covers nowadays the whole range between the theoretical aspects and practical implementations of distributed systems, as well as experimentation [...]

Lock Oscillation: Boosting the Performance of Concurrent Data Structures

The paper "Lock Oscillation: Boosting the Performance of Concurrent Data Structures" by Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH has been accepted for the Conference on Principles of Distributed Systems (OPODIS 2017). The paper is based on FORTH's work in ExaNoDe on atomics and the GSAS environment. Abstract: In combining-based synchronization, two main parameters that affect performance are the combining degree of the synchronization algorithm, i.e., the average number of requests that each combiner serves, and the number of expensive synchronization primitives (like CAS, Swap, Fetch&Add, etc.) that it performs. The value of the first parameter must [...]

ExaNoDe in the 2017 European HPC Handbook

ExaNoDe, part of the global European exascale R&D effort, is presented in the European HPC Handbook released in the context of SC17. The Handbook includes summaries of all the European HPC projects (technology and applications), with an emphasis on their international collaboration potential. A pdf version of the Handbook is available here SC17 will include a BoF session called "European Exascale Projects and Their Global Contributions" where a holistic view of Europe's HPC development will be presented. More information about the BoF session is available here

HiPEAC conference , 22-24 January 2018, Manchester

The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems. The 13th HiPEAC conference will take place in Manchester, UK from Monday, January 22 to Wednesday, January 24, 2018. Associated workshops, tutorials, special sessions, several large poster session and an industrial exhibition will run in parallel with the conference. At HiPEAC18 ExaNoDe will be presented as part of the full-day workshop “Towards Exascale HPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects”. More information can be found here: https://www.hipeac.net/2018/manchester/

ARM Research Summit, 11-13 September 2017, Robinson College, Cambridge

The second annual Arm Research Summit was an academic summit to discuss future trends and disruptive technologies across all sectors of computing. It took place in Cambridge from 11 to 13 September 2017, and was hosted at Robinson College. The Summit included talks from the leaders in their research fields, demonstrations, networking opportunities and the chance to interact and discuss projects with members of Arm Research. The project coordinator Denis Dutoit (CEA) presented ExaNoDe as part of the Collaborative Research Projects Workshop which took place on 13 September. More information can be found here: https://developer.arm.com/research/summit

Euromicro DSD/SEAA 2017, 30 August – 1 September 2017, Vienna, Austria

Euromicro DSD/SEAA 2017, 30 August - 1 September 2017, Vienna, Austria The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from specification down to micro-architectures, digital circuits and VLSI implementations. The event also dedicates a Special Session for European projects, discussing the aims, problems to be addressed and issues to be solved, proposed approaches and/or results achieved till now. Kevin Pouget, virtualization engineer at Virtual Open System, presented the paper "Paving the way towards a highly energy-efficient and highly integrated compute node for [...]

D43D’2017 9th Workshop on Design for 3D Silicon Integration, Minatec, Grenoble, France, 26-27 June

D43D is a workshop on Design for 3D Silicon Integration that brings together experts from both industry and academia, and covers topics including: 3D technology, 3D architecture for computing, interconnect architectures, design methodologies and tools. Denis Dutoit from CEA Leti presented emerging architectures for computing with 3D silicon integration which are investigated in ExaNoDe.

High Performance Computing and Open Source Linux Technical ExcellenceSymposium in Grenoble, 20th-24th March

Presentation of ExaNoDe by Denis Dutoit (CEA) Denis Dutoit presented the ExaNoDe project at the 9th edition of the High Performace Computing and Open Source Linux Technical Excellence Symposium in Grenoble. The event included lab sessions and numerous demonstrations, gathering best in class speakers in the HPC community. The agenda of the event is available here

ExaNoDe, ExaNeSt and ECOSCALE signed “Memorandum of Understanding”

On March, 17, 2017 a "Memorandum of Understanding" (MoU) between the FET-HPC projects ExaNoDe, ExaNeSt and ECOSCALE was signed by the three project coordinators. The purpose of this MoU is to strengthen the links between the projects and to exploit common activities and synergies in a consistent cross-project schedule. More information can be found here.

ExaNoDe at Super Computing 2016

On November 13 – 18 2016 ExaNoDe will be represented by EXDCI at the Super Computing 2016 conference in Salt Lake City. EXDCI has organized a BoF session to present European Exascale projects and their international cooperation potential, and will share a booth with PRACE. ExaNoDe will be represented in both initiatives with presentations and information gathered by EXDCI through a set of surveys.

Second cross-project joint workshop with ExaNeSt and ECOSCALE

After the successful exchange during the first workshop, the three projects decided to organize a second joint meeting in co-location with the Computing Systems Week (CSW) in Dublin on Nov 7-9 2016. Compared to the first workshop, the second one has a broader point of view: besides applications, it includes also system software, hardware prototypes and reconfigurable accelerators with the goal of strengthening the potential cooperation directions and start an actual exchange of information and outputs.

ExaNoDe participates in the first joint workshop on Applications with ExaNeSt and ECOSCALE projects

On September 20-21 the three twin H2020 projects ExaNoDe, ExaNeSt and ECOSCALE have organized the first cross-project joint workshop focusing on Applications. The workshop was held in Trieste and hosted by Istituto Nazionale di Astro Fisica (INAF). The main goal of this two days meeting was first to present the work performed within the three projects, and then to identify possible points of cooperation in the fields of use-case applications, programming models and reconfigurable accelerators and their virtualization.

ExaNoDe project presentation at European HPC Summit Week 2016

May 10th, 2016 – The ExaNoDe project was presented at the European HPC Summit Week 2016 (May 9 – 12, 2016) in Prague, Czech Republic, in a workshop organised by the EXDCI (European Extreme Data & Computing Initiative) Coordination and Support Action. The workshop’s target was to bring together the Research & Development & Innovation projects and Centres of Excellence (CoEs) funded within the European Commission research programme developing technologies and user environments for exascale computing. Dr. Denis Dutoit, the ExaNoDe Project Coordinator, explained the ExaNoDe approach and highlighted possibilities for collaboration and take-up of technologies in line with the HPC [...]

ExaNoDe selects underlying technology components

Barcelona, 5 April 2016 The European project ExaNoDe (European Exascale Processor Memory Node Design) will develop a compute element aimed towards Exascale computing. ExaNoDe will build a node-level prototype with technologies that exhibit a significant potential for Exascale computing. The building blocks are heterogeneous compute elements (ARM-v8 low-power processors and FPGAs), 3D active interposers for compute density and UNIMEM, an advanced memory scheme for low-latency, high-bandwidth memory access. ExaNoDe will use a commercially available ARM-v8 based computing architecture. CEA-Leti has developed a state-of-the-art silicon interposer which will be used in the ExaNoDe project. This interposer exploits CEA’s integration expertise, forming [...]

ExaNoDe Research Exhibit – SC15 Emerging Technologies

ExaNoDe was selected as one of the research exhibits in the “Emerging Technologies” Technical Program track of the SC15 conference that took place in Austin, Texas. Link: sc15.supercomputing.org/program/emerging-technologies The Emerging Technologes track showcased innovative technologies considered to have the potential to significantly change and extend the world of HPC in the next five to fifteen years. A particular focal point was emerging System-on-a-Chip (SoC) technologies for HPC. ExaNode presented an overview of the project, the technology targets and an overview of the ongoing architectural design development.

Project Kick-Off Meeting at CEA, Grenoble

All project participants came together for the first project meeting, which gave the opportunity for a review of projects plans and objectives and for cross-theme discussions and technology presentations.

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