The program of the Exascale HPC Workshop at HiPEAC 2018 has been published:

Update: ExaNoDe presentations are online

Tuesday 23 January 2018 full day (10:00-17:30)

This Workshop (part of HiPEAC 2018) will present the main results from ExaNoDE and its two sibling projects, ExaNeSt, and EcoScale, which are at the end of their 2nd year, each; also, the newly-started follow-up FET-HPC project, EuroEXA, will present its plans for the next 3 years. The four projects cover, collectively, the following areas, which this Workshop will also cover:

  • High Performance Computing and Architectures, and their Evaluation
  • 2.5D Integration, Packaging, and Cooling Technologies
  • Novel, Unified, and Reconfigurable Accelerators and Tools to use them
  • Low-power Processors and die-to-die Communication
  • Low latency, Unified and Resilient Interconnects
  • Task-based Programming Models and Runtime Systems
  • Virtualization for HPC
  • Fast Communication & Systems Software: MPI, PGAS, VMs, Libraries, Management
  • HPC Extreme Scale Demonstrators
  • Storage for HPC
  • Exascale-class Applications and Mini-apps enabling System Co-design.


10:00 – 11:00   Keynote:

• The Challenges of Exascale and a Shared Vision on Technology Advances – by John Goodacre, Professor of Computer Architectures, The University of Manchester

11:30 – 13:00   Memory, Communication, and Accelerator Virtualization:

• Use-cases for Remote Memory in the UNIMEM Architecture – by Nikolaos D. Kallimanis e.a.; FORTH, Heraklion, Crete.
• Virtualization for HPC – by Kevin Pouget e.a.; Virtual Open Systems.
• UNIMEM and UNILOGIC Architectures for local/remote Sharing of Resources – by Konstantinos Georgopoulos e.a.; TSI, Chania, Crete; and Chalmers Univ. of Tech.
• Reconfigurable Accelerators: OpenCL Runtime and FPGA Design Tools – by Dirk Koch, Konstantin Bakanov, e.a.; University of Manchester; Politecnico di Torino; Queen’s University of Belfast.

14:00 – 15:30   Technology and Architecture:

• 3D-IC Design Solution for Modular Integration of Chiplet over Silicon Interposer – by Pierre-Yves Martinez e.a.; CEA, France; and University of Sherbrooke.
• Ultra-Low Swing Transceiver for Energy Efficient Communication in 2.5-D Integrated Systems – by Przemyslaw Mroszczyk and Vasilis Pavlidis; University of Manchester
• Compact Packaging and Liquid Cooling Technology for Exascale – by Peter Hopton, Fabien Chaix, e.a.; Iceotope, UK; and FORTH, Heraklion, Crete.
• Multi-tier Interconnect and Mechanisms for Exascale Communication – by Javier Navaridas, Piero Viciny, e.a.; University of Manchester; INFN, Roma; U. P. Valencia; and FORTH, Heraklion, Crete.

16:00 – 17:30   Programming Environment, Applications and Evaluation:

• ExaNoDe Programming Environment to Exploit ARM, UNIMEM and FPGA’s – by Babis Chalios e.a.; Barcelona Supercomputing Center; e.a.
• Exploiting the ExaNeSt Communication Primitives for a High Performance MPI Library– by Antonios Psistakis e.a.; FORTH, Heraklion, Crete.
• Re-Engineering Astrophysical Codes for the Exascale Era – by Luca Tornatore, David Goz, e.a.; INAF, Italy; and Politecnico di Torino.
• EuroEXA: co-Design, Demonstration, and Evaluation using a rich set of Exascale-class Applications – by Paul Carpenter e.a.; Barcelona Supercomputing Center; e.a.

Organizing Committee:

• Eduard Ayguadé, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya
• Luca Benini, ETH Zurich
• Denis Dutoit, CEA, France
• Georgios Goumas, National Technical University of Athens / Inst. of Communication & Computer Systems
• Manolis Katevenis, FORTH and University of Crete
• Luciano Lavagno, Politecnico di Torino
• Mikel Luján, University of Manchester
• Iakovos Mavroidis, Technical University of Crete / Telecommunication Systems Institute