European Exascale Processor & Memory Node Design|info@exanode.eu

General news

Press release: ExaNode project produced groundbreaking compute unit prototype for Exascale

The ExaNode Project finished successfully in summer 2019 The project has built a groundbreaking compute unit prototype paving the way to tomorrow’s  exascale supercomputers, those capable of performing a billion billion calculations per second, or ten times faster than today’s most powerful computers. Read more in our general and technical press releases: Press release – with technical details (PDF) Press release – for the general public (PDF)

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VOSYS presentation on virtualization for HPC at COMPAS

Kevin Pouget from Virtual Open Systems presented the ExaNoDe work on virtualization at the COMPAS conference: OpenCL accelerator API remoting for HPC computing, and virtual machine live and incremental checkpointing. He presented a poster and gave a talk in the industrial session of the COMPAS conference. COMPAS, a French-speaking conference aimed at gathering senior researchers with PhD students and industrials around the topics of parallel computing, systems and architectures, took place in Toulouse, France, 3-6th of July.

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EuroPar 2018, August 29-31, Turin

The paper “HPC benchmarking: scaling right and looking beyond the average” by ExaNoDe partner BSC was accepted for EuroPar 2018 taking place in Turin, August 29-31, 2018. Euro-Par is the prime European conference covering all aspects of parallel and distributed processing, ranging from theory to practice, from small to the largest parallel and distributed systems and infrastructures, from fundamental computational problems to full-fledged applications, from architecture, compiler, language and interface design and implementation, to tools, support infrastructures, and application performance aspects. Euro-Par’s unique organization into topics provides an excellent forum for focused technical discussion, as well as interaction with a [...]

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HPC benchmarking: scaling right and looking beyond the average

The paper “HPC benchmarking: scaling right and looking beyond the average” by Milan Radulovic, Kazi Asifuzzaman, Paul Carpenter, Petar Radojković and Eduard Ayguadé from ExaNode Partner BSC will be presented at EuroPar 2018 in Turin, August 2018. Abstract: Designing a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads, and which quantifies the main performance bottlenecks. In this paper, we execute seven production HPC applications on a production HPC platform, and analyse key performance bottlenecks: FLOPS performance and memory bandwidth congestion, [...]

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An EfficientWait-free Resizable Hash Table

The paper “An EfficientWait-free Resizable Hash Table” by Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH has been accepted by 30th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2018) taking place from July 16-18 in Vienna. The paper builds on FORTH’s work in ExaNoDe on Lock Oscillation. Abstract: This paper presents an efficient wait-free resizable hash table. To achieve high throughput at large core counts, our algorithm is specifically designed to retain the natural parallelism of concurrent hashing, while providing wait-free resizing. An extensive evaluation of our hash table shows that it provides an unprecedented combination of [...]

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The paper “Mismatch Compensation Technique for Inverter-Based CMOS Circuits” was accepted for the isQED 2018 conference

The paper "Mismatch Compensation Technique for Inverter-Based CMOS Circuits" by  Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester was accepted for the isQED 2018 conference. Abstract: This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down [...]

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The paper “Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems” was accepted for the ISCAS 2018 conference

The paper "Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems" by Przemyslaw Mroszczyk and Vasilis F. Pavlidis from ExaNoDe partner University of Manchester was accepted for the ISCAS 2018 conference. Abstract: Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication, A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant [...]

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Program of the Exascale HPC Workshop at HiPEAC 2018 has been published

The program of the Exascale HPC Workshop at HiPEAC 2018 has been published: Update: ExaNoDe presentations are online Tuesday 23 January 2018 full day (10:00-17:30) This Workshop (part of HiPEAC 2018) will present the main results from ExaNoDE and its two sibling projects, ExaNeSt, and EcoScale, which are at the end of their 2nd year, each; also, the newly-started follow-up FET-HPC project, EuroEXA, will present its plans for the next 3 years. The four projects cover, collectively, the following areas, which this Workshop will also cover: […]

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Lock Oscillation: Boosting the Performance of Concurrent Data Structures

The paper "Lock Oscillation: Boosting the Performance of Concurrent Data Structures" by Panagiota Fatourou and Nikolaos D. Kallimanis from ExaNoDe partner FORTH has been accepted for the Conference on Principles of Distributed Systems (OPODIS 2017). The paper is based on FORTH's work in ExaNoDe on atomics and the GSAS environment. Abstract: In combining-based synchronization, two main parameters that affect performance are the combining degree of the synchronization algorithm, i.e., the average number of requests that each combiner serves, and the number of expensive synchronization primitives (like CAS, Swap, Fetch&Add, etc.) that it performs. The value of the first parameter must [...]

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ExaNoDe in the 2017 European HPC Handbook

ExaNoDe, part of the global European exascale R&D effort, is presented in the European HPC Handbook released in the context of SC17. The Handbook includes summaries of all the European HPC projects (technology and applications), with an emphasis on their international collaboration potential. A pdf version of the Handbook is available here SC17 will include a BoF session called "European Exascale Projects and Their Global Contributions" where a holistic view of Europe's HPC development will be presented. More information about the BoF session is available here

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ExaNoDe, ExaNeSt and ECOSCALE signed “Memorandum of Understanding”

On March, 17, 2017 a "Memorandum of Understanding" (MoU) between the FET-HPC projects ExaNoDe, ExaNeSt and ECOSCALE was signed by the three project coordinators. The purpose of this MoU is to strengthen the links between the projects and to exploit common activities and synergies in a consistent cross-project schedule. More information can be found here.

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Second cross-project joint workshop with ExaNeSt and ECOSCALE

After the successful exchange during the first workshop, the three projects decided to organize a second joint meeting in co-location with the Computing Systems Week (CSW) in Dublin on Nov 7-9 2016. Compared to the first workshop, the second one has a broader point of view: besides applications, it includes also system software, hardware prototypes and reconfigurable accelerators with the goal of strengthening the potential cooperation directions and start an actual exchange of information and outputs.

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ExaNoDe participates in the first joint workshop on Applications with ExaNeSt and ECOSCALE projects

On September 20-21 the three twin H2020 projects ExaNoDe, ExaNeSt and ECOSCALE have organized the first cross-project joint workshop focusing on Applications. The workshop was held in Trieste and hosted by Istituto Nazionale di Astro Fisica (INAF). The main goal of this two days meeting was first to present the work performed within the three projects, and then to identify possible points of cooperation in the fields of use-case applications, programming models and reconfigurable accelerators and their virtualization.

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ExaNoDe project presentation at European HPC Summit Week 2016

May 10th, 2016 – The ExaNoDe project was presented at the European HPC Summit Week 2016 (May 9 – 12, 2016) in Prague, Czech Republic, in a workshop organised by the EXDCI (European Extreme Data & Computing Initiative) Coordination and Support Action. The workshop’s target was to bring together the Research & Development & Innovation projects and Centres of Excellence (CoEs) funded within the European Commission research programme developing technologies and user environments for exascale computing. Dr. Denis Dutoit, the ExaNoDe Project Coordinator, explained the ExaNoDe approach and highlighted possibilities for collaboration and take-up of technologies in line with the HPC [...]

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ExaNoDe selects underlying technology components

Barcelona, 5 April 2016 The European project ExaNoDe (European Exascale Processor Memory Node Design) will develop a compute element aimed towards Exascale computing. ExaNoDe will build a node-level prototype with technologies that exhibit a significant potential for Exascale computing. The building blocks are heterogeneous compute elements (ARM-v8 low-power processors and FPGAs), 3D active interposers for compute density and UNIMEM, an advanced memory scheme for low-latency, high-bandwidth memory access. ExaNoDe will use a commercially available ARM-v8 based computing architecture. CEA-Leti has developed a state-of-the-art silicon interposer which will be used in the ExaNoDe project. This interposer exploits CEA’s integration expertise, forming [...]

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Project Kick-Off Meeting at CEA, Grenoble

All project participants came together for the first project meeting, which gave the opportunity for a review of projects plans and objectives and for cross-theme discussions and technology presentations.

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